A plurality of chips that are layered one on top of the other and electrically connected to each other through connecting members such as through silicon vias (TSV) or micro bumps is referred to as “three-dimensional integrated circuit.” In a three-dimensional integrated circuit, each connecting member has a diameter within the range from several μm to several tens of μm, and occupies a tiny area of a chip. Accordingly, connecting members may be greater in number than external pins of the chip, and in particular, can be distributed throughout the chip.
In the manufacturing process of three-dimensional integrated circuits, the thickness of each chip is reduced by a polishing process such as Chemical Mechanical Polish (CMP). As the result of the polishing process, some chips will be as thin as several μm. The reason for making chips thin is as follows. In the case where connecting members are TSVs, the depth of each TSV becomes smaller with a reduced thickness of a chip. This reduces a time period required for forming the TSVs. As a result, the manufacturing cost of the chip is reduced. In addition, a three-dimensional integrated circuit (chip package) that is to be mounted on a mobile phone and the like requires a layered structure of a plurality of chips, but on the other hand, is subject to a restriction on the thickness of its entire package. Therefore, the thickness of each chip has to be small to reduce the thickness of the entire package.
Chips with a reduced thickness warp. For example, Patent Literature 1 discloses that thinner chips more greatly warp. Further, Non-Patent Literature 1 discloses experimental data on warpage of a silicon wafer. Warpage of chips leads to the following problems. During manufacture of three-dimensional integrated circuits, chips are separately manufactured and bonded to each other by adhesive layers or the likes. If the chips warped at the time of bonding, increase of the distances between the chips might cause a defect to occur in a connecting member. The probability of occurrence of a defect in a connecting member is not negligible in the first place since the structure of each connecting member is fine and minute, and in addition the number of connecting members is very large. If the chips were designed without considering possible occurrence of a faulty connection, a chip that would happen to have a faulty connection would have to be discarded as a defective product. That is, the yield of chips would decrease by the probability of occurrence of a faulty connection. As a result, it is difficult to further reduce the manufacturing cost of the chips.
As a technology for preventing a decrease in the yield of circuitry caused by connection failures in wiring, a redundant technology is known (see Patent Literature 2, for example). “Redundant technology” is a technology for preparing a redundant circuit such as a wire and a cell embedded in circuitry and, when a wire or cell of the circuitry is defective, using the redundant circuit instead of the defective wire or cell. In a semiconductor memory device disclosed in Patent Literature 2, redundant selection wires are prepared in addition to selection wires of memory cells. Further, switches are located between the selection wires and external signal lines. The switches connect the redundant selection wires, instead of the selection wires, to the external signal lines. With this structure, when any of the selection wires is defective, one of the redundant selection wires is connected to the external signal lines, instead of the defective selection wire. As a result, the semiconductor memory device need not to be discarded in more cases even when any of the selection wires is defective, and accordingly, the yield of semiconductor memory devices avoids decreases caused by defective selection wires.